First Problem
In a digital phase lock loop, the output of a down counter is stabilized to an input (incoming) clock signal by changing the counter modulus. As the frequency of the input clock signal decreases, the counter modulus must increase to maintain synchronization therewith. Unfortunately, as the counter modulus increases, a given change in counter modulus tends to have less and less effect, so that the digital phase lock loop becomes slower in its response to changes in the input clock frequency or phase. Eventually, after the counter modulus has increased to a very large number (to handle a relatively lower input clock frequency), the digital phase lock loop can no longer respond in a timely manner to differences between the input clock and output clock phase or frequency, and therefore it cannot synchronize the two together effectively. Phase lock loops generally are limited to a given bandwidth of input clock frequencies for which phase lock can be achieved. Thus, a first problem is how to increase the bandwidth capability of a digital phase lock loop beyond this seemingly fundamental limitation.